The three stages of reconfigurable computing – stage 2
The second in the 3-part series of articles by Dan Joe, where he explores the various stages of reconfigurable computing.
The three stages of reconfigurable computing – stage 1
The first in the 3-part series of articles by Dan Joe, where he explores the various stages of reconfigurable computing.
Packet Capture As a Service
A blog article by Alex Agerholm, who explains and delves into the concept of packet capture as a service in a virtualized environment.
VPP – What performance to expect from a 2x100GbE NIC
VPP - Vector Packet Processing is a open-source project with high community activity. How does it perform running on Napatech NICs?
QSFP-DD, the new ‘kid’ on the block
As a continuation to his previous blog - “Flexible Pluggable Front Port Technology”, in the current blog Claus Ek focuses on the latest addition to the QSFPx form factor family - the QSFP-DD.
Why do you need 100G network traffic replay?
In his latest blog, Sven talks about the network traffic replay at 100G and its benefits in a test scenario.
In the Age of FPGA
FPGA has shown that it can provide significant acceleration and a high level of reconfigurability and doing all that with an efficient compute power per watt.
So where does all this lead and who is the winner?
Is it time to reimagine the NFV infrastructure?
In the run-up to SDN World Congress in The Hague, it is interesting to note that it was at this very show in Dusseldorf 5 years ago that the original NFV whitepaper was first presented. How time flies!
100GbE line-rate traffic generation using TRex and Napatech NICs
TRex is used to show that 64 byte packet generation at 100Gbps on a 100GbE link is achievable using a standard server and a Napatech NIC.
Flexible Pluggable Front Port Technology
I am writing this blog article in continuation of my previous blog – “Future-proof FPGA platforms the longevity and upgradability”. In this blog entry, I discuss the available pluggable front port technology, complementing the flexible properties of the described future-proof FPGA-based SmartNICs.