Leveraging Napatech’s industry-proven hardware, Link-Programmable™ provides OEMs and end users with a solid platform for deploying their own custom FPGA computation solutions.
Open Standard Servers
Peak performance at minimal cost
Ethernet Front Port Compliance
Error-free uninterrupted operation
Event Handling & System Monitoring
Seamless integration – maximized uptime
Thermal Performance
Optimized rack-space utilization
Regulatory Compliance
Quick integration with no delays
Shock & Vibration Robustness
Strong resilience to rough environments
PCI Compliance
Proven uncompromising quality
Rivaling clustered HPC at a fraction of the cost
Link-Programmable™ brings massive parallel processing capacity to compute intensive applications. The hardware is designed to accommodate thermal and slot-size constraints, enabling 8+ cards to sit adjacent in a single COTS server. Through ultra-highspeed interconnects, the cards can distribute workloads across FPGAs, providing parallel processing capacity comparable to clustered high performance computing (HPC) solutions at a fraction of the cost.
Ruggedized and industry-proven hardware
Meticulously designed, validated and compliance-tested to minimize integration risks in the server environment, Link-Programmable™ enables OEMs and end users to focus their efforts on the target application, removing complexity and uncertainty from the integration process.
With ~300,000 hours of mean time between failures (MTBF), our hardware ensures uninterrupted,
error-free operation for many years ahead – as validated by our long-term loyal customer base.
Link-Programmable™ Development Kit
FPGA Customization
- Provides access to programmable logic on Napatech SmartNICs.
- Enables users to create and deploy custom packet processing pipelines directly on the NIC.
P4 and VHDL Support
- Offers a framework to develop network functions using P4, a high-level language for programming protocol-independent packet processors.
- Also supports VHDL for more complex and fine-grained FPGA programming.
Reference Designs
- Comes with example designs and IP blocks (e.g., for packet parsing, filtering, flow classification).
- Accelerates development by offering building blocks for common networking tasks.
Integration Tools
- Includes APIs and drivers to integrate FPGA applications with host software.
- Supports integration with DPDK, Linux, and Windows environments.
Use Cases
- Network monitoring and telemetry.
- Cybersecurity (e.g., deep packet inspection, intrusion detection).
- Low-latency financial trading networks.
- Custom inline network processing like traffic shaping or firewalling.
Performance
- Leverages the high throughput and low latency of Napatech’s FPGA-based SmartNICs to offload and accelerate packet processing tasks from the CPU.
Napatech SmartNIC features
To generate and control the airflow, the Napatech design contains a blower that takes in air from the top and bottom of the card, thereby doubling the amount of air and ensuring superior cooling.
Benefits
- Durable design for extended real-life operation
- Free choice of server platform
- Reduced noise and power-consumption as server-fans can run at minimum speed
- Freedom to pack unlimited FPGA SmartNICs into a standard server
Specs
- No airflow dependency to server
- Well-defined cooling of all critical components
- Guaranteed device hot spot temperatures
- Maximized airflow, ensuring optimal thermal performance
- Dissipated energy exhaled outside server through front plate cutouts
- Significant reduction in temperature drop between FPGA die and heat sink surface
- Mechanical stiffener enabling higher screw torque for fastening heatsink to the PCB
Compliance
Napatech upholds the highest quality, environmental and safety standards, and complies with all applicable regulations across regions. This helps our customers to realize a seamless integration without delays – and ensures error-free operation throughout the product life cycle.
Ethernet Front Port Compliance
All Napatech designs maximize mechanical and electrical front port margin, securing trouble-free operation with the optical or electrical modules of the customer’s choice.
The thermal design is validated dissipating the maximum power level as standardized for the given form factor. Margin on the data interface has been optimized tuning the equalization parameters of the transceivers hosting the front port channel, maximizing EYE margin to the relevant standard.
EMC Compliance
All Napatech designs have passed EMC compliance testing for major regions, including Europe and North America. By ensuring compliance as an integral part of the design, the risk of delays is eliminated. Moreover, the EMC testing has been performed in a mainstream server, potentially directly applicable to the use case.
Environmental Compliance
The end product must adhere to regional environmental legislation. To enable trouble-free server integration, Napatech hardware is manufactured using only materials that fully comply with the current RoHS, REACH and proprietary Tier 1 legislation.
Full compliance from early inception eliminates the risk delays and product withdrawal due to authority intervention.
Event Handling & System Monitoring
To become an integral part of the server environment and maximize uptime, the hardware needs to monitor and expose key performance metrics to the application during operation. Napatech hardware monitors the following metrics:
- Blower speed
- Hot spot temperatures
- Key supply voltages and currents
- PCI protocol events
- General system events
PCI Compliance
With the PCI interface dictated by the server plane, the hardware maximizes mechanical and electrical PCI margin, ensuring trouble-free operation in the server and server slot(s) of the customer’s choice. All designs have passed relevant PCI-SIG tests.
Safety Compliance
To enable trouble-free server integration, Napatech hardware is fully compliant with all applicable safety standards.
By ensuring safety compliance as an integral part of the SmartNIC design, the risk of delays is eliminated. Compliance testing is performed in a mainstream server, potentially directly applicable to the use case.
Conflict Minerals Compliance
To ensure quick and trouble-free server integration, Napatech hardware is manufactured using only materials that fully comply with the relevant Conflict Mineral Legislation. For US based integrators, this facilitates submission of the mandatory Conflict Mineral report to SEC.
Shock & Vibration Robustness
Many server environments expose the card to substantial shock and vibration, predominantly during the transportation phase. To ensure trouble-free server integration and operational robustness throughout the product life cycle, validated design aspects include:
- Cooling enclosure for superior mechanical stiffness
- Key exposed components are under-filled (glued) to the PCB
- Shock robustness validated against JESD22-B110A
- Vibration robustness validated against ASTM D4169-09
Hardware highlights and specifications
| TECH SPECS | NT200A02 SmartNIC | NT400D11 SmartNIC |
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| Environment for NT400D11-SCC (active cooling) |
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| Environment for NT400D11-NEBS (passive cooling) |
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| Regulatory Approvals and Compliances |
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Network Security (e.g., IDS/IPS, DPI, Packet Filtering)
Ideal for: Intrusion detection systems (Snort, Suricata), deep packet inspection (DPI), and inline threat mitigation. FPGAs can inspect and filter packets at wire speed with minimal latency—critical for real-time security enforcement.
Network Monitoring and Analytics
Ideal for: Network traffic capture, NetFlow/IPFIX generation, packet recording (PCAP), and telemetry. Accurate timestamping, zero packet loss, and hardware-based flow classification allow scalable monitoring at 100G+.
Network Function Virtualization (NFV)
Ideal for: Virtual routers, firewalls, load balancers, and UPFs in telecom and enterprise networks. Offloads packet processing tasks (parsing, flow table lookups, forwarding) from CPUs, enabling higher VNF density and performance.
Financial Trading Systems
Ideal for: Market data feed handling, latency monitoring, and compliance logging. Deterministic low-latency and nanosecond-accurate timestamping are essential for high-frequency trading (HFT).
5G/Telecom Infrastructure (UPF, vRAN)
Ideal for: User plane function (UPF) acceleration, GTP-U tunneling, RAN disaggregation. Telecom packet processing demands predictable performance and high throughput, which FPGAs handle efficiently.
AI/ML Preprocessing for Network Data
Ideal for: Real-time data filtering and feature extraction for feeding machine learning models. Hardware acceleration of data normalization, packet sampling, and metadata extraction before AI inference.
Custom Protocol Processing
Ideal for: Proprietary or experimental networking protocols used in R&D or defense. Reprogrammable logic allows implementation of custom parsing, state machines, and protocol behaviors.
Supported Open-Source Applications
Napatech SmartNICs support a variety of open-source tools, especially in the fields of network monitoring, security, and traffic analysis. Napatech provides hardware-accelerated drivers, APIs, and plugins that allow integration with these tools, ensuring they can operate at high speed and with minimal packet loss.
FPGA Development
